1. Field of the Invention
The present invention relates to a geometry translation processor incorporated in a floating-point processor, for carrying out geometry translation when drawing graphics on a display.
2. Description of the Prior Art
When drawing a polygon on a display, it is necessary to translate the three-dimensional coordinates of each vertex of the polygon into two-dimensional ones. The translation is achieved by calculating the product of a 4-by-4 matrix and a 4-element vector. After the translation, each vertex of the polygon is checked to see if it is within a display area, to determine whether the vertex must be clipped or displayed as it is.
For example, an output coordinate vector (x', y', z', w') is obtained as the product of an input coordinate vector (x, y, z, 1) and the following matrix: ##EQU1##
The product is calculated as follows: ##EQU2##
The calculation is executed at high speed with four multiply-add calculation units by operating them four times in parallel. After translation, every coordinate is checked to see if it is within a display area, to determine whether it must be clipped or displayed as it is.
A translated point having the coordinates (x', y', z', w') is within the display area, if the following are satisfied: EQU -.vertline.w'.vertline.&lt;x'&lt;.vertline.w'.vertline. (1) EQU -.vertline.w'.vertline.&lt;y'&lt;.vertline.w'.vertline. (2) EQU -.vertline.w'.vertline.&lt;z'&lt;.vertline.w'.vertline. (3)
Checking a given point to see if it is within a display area is called a clipping test.
If a given point is out of a display area, the following are tested: EQU if .vertline.x'.vertline.&lt;-.vertline.w'.vertline. then the point is out in a negative x-direction (4) EQU if .vertline.x'.vertline.&gt;.vertline.w'.vertline. then the point is out in a positive x-direction (5) EQU if .vertline.y'.vertline.&lt;-.vertline.w'.vertline. then the point is out in a negative y-direction (6) EQU if .vertline.y'.vertline.&gt;.vertline.w'.vertline. then the point is out in a positive y-direction (7) EQU if .vertline.z'.vertline.&lt;-.vertline.w'.vertline. then the point is out in a negative z-direction (8) EQU if .vertline.z'.vertline.&gt;.vertline.w'.vertline. then the point is out in a positive z-direction (9)
The clipping test is carried out on each vertex of a given polygon after geometry translation. When drawing a polygon having n vertexes, the clipping test is carried out n times to test every vertex. If every vertex of the polygon is in a display area, the polygon is drawn as it is. If any one of the vertexes is out of the display area, the polygon is partly clipped and displayed. If every vertex is out of the display area, there will be two cases. In one case, every vertex is out of the display area in a given direction, to satisfy, for example, the expression (4). In this case, the polygon is not drawn. In the other case, one vertex may satisfy the expression (4) and the others the expression (5). Then, the polygon is partly clipped and displayed.
FIG. 1 shows a geometry translation processor for carrying out geometry translation and clipping tests according to a prior art. This processor is incorporated in a floating-point processor.
The floating-point processor is a coprocessor, and therefore, instructions for the processor are fetched and decoded by a main processor. Conditional branching is carried out by the main processor in response to a signal TRUE/FALSE sent from the coprocessor.
The geometry translation processor has a 128-bit source bus 1, a 128-bit source bus 2, a 128-bit destination bus 3, a register block 4, and operation units 7x, 7y, 7z, and 7w. Bit lines of each of the 128-bit buses are divided into four groups each including 32 bit lines. The groups are called x-, y-, z-, and w-groups.
FIG. 2 shows the details of the register block 4 containing 64 registers R0 to R63. The x-group bit lines of the source bus 2 and destination bus 3 are connected to the registers R0, R4, R8, and the like whose register numbers are each divisible by four. The y-group bit lines of the buses 2 and 3 are connected to the registers R1, R5, R9, and the like whose register numbers provide each a remainder of 1 when divided by four. The z-group bit lines of the buses 2 and 3 are connected to the registers R2, R6, R10, and the like whose register numbers provide each a remainder of 2 when divided by four. The w-group bit lines of the buses 2 and 3 are connected to the registers R3, R7, R11, and the like whose register numbers provide each a remainder of 3 when divided by four. The bit lines of the source bus 1 are connected to all registers of the register block 4, to form a crossbar structure.
FIG. 3 shows the details of the operation units 7x, 7y, 7z, and 7w. These units are multiply-add calculation units FMACx, FMACy, FMACz, and FMACw, which are capable of calculating multiply-add, multiplication, addition, and subtraction in parallel. A special operation such as comparison is carried out by the unit 7w.
The units 7x to 7w calculate a 4-by-4 matrix at high speed in geometry translation. Examples of instructions and a program used for calculating a matrix will be explained.
Any numeral having a prefix of "R" represents a register number.
FMUL: Carry out four multiplications in parallel
Example: FMUL R20-R23, R16, R0-R3
R20.rarw.R16.times.R0 PA1 R21.rarw.R16.times.R1 PA1 R22.rarw.R16.times.R2 PA1 R23.rarw.R16.times.R3 PA1 R20.rarw.R20+R16.times.R0 PA1 R21.rarw.R21+R16.times.R1 PA1 R22.rarw.R22+R16.times.R2 PA1 R23.rarw.R23+R16.times.R3 PA1 FCMP: Compare floating-point numbers with each other. A result is sent as a signal TRUE/FALSE to the main processor. PA1 FCMP eq R0, R1; if R0=R1 then TRUE, and if not then FALSE PA1 FCMP ne R0, R1; if not R0=R1 then TRUE, and if R0=R1 then FALSE PA1 FCMP gt R0, R1; if R0&gt;R1 then TRUE, and if not then FALSE PA1 FCMP le R0, R1; if R0&lt;=R1 then TRUE, and if not then FALSE PA1 FCMP lt R0, R1; if R0&lt;R1 then TRUE, and if not then FALSE PA1 FCMP ab R0, R1; if R0&gt;32 R1 then TRUE, and if not then FALSE PA1 Vertex coordinates of the triangle before translation are stored in the following registers: PA1 Vertex 1: (R0, R1, R2, R3) PA1 Vertex 2: (R4, R5, R6, R7) PA1 Vertex 3: (R8, R9, R10, R11) PA1 Vertex 1: (R32, R33, R34, R35) PA1 Vertex 2: (R36, R37, R38, R39) PA1 Vertex 3: (R40, R41, R42, R43) PA1 Start of program list 1; PA1 Coordinate translation of vertex 1 PA1 FMUL R32-R35, R0, R16-R19 PA1 FMAC R32-R35, R1, R20-R23 PA1 FMAC R32-R35, R2, R24-R27 PA1 FMAC R32-R35, R3, R28-R31; PA1 Coordinate translation of vertex 2 PA1 FMUL R35-R39, R4, R16-R19 PA1 FMAC R35-R39, R5, R20-R23 PA1 FMAC R36-R39, R6, R24-R27 PA1 FMAC R36-R39, R7, R28-R31; PA1 Coordinate translation of vertex 3 PA1 FMUL R40-R43, R8, R16-R19 PA1 FMAC R40-R43, R9, R20-423 PA1 FMAC R40-R43, R10, R24-R27 PA1 FMAC R40-R43, R11, R28-R31; PA1 Clipping test with w being positive; PA1 Vertex 1 PA1 FCMP gt R32, R35; if x&gt;w at vertex 1 then PA1 BCT label; jump to clipping process PA1 FCMP gt R33, R35; if y&gt;w at vertex 1 then PA1 BCT label; jump to clipping process PA1 FCMP gt R34, R35; if z&gt;w at vertex 1 then PA1 BCT label; jump to clipping process PA1 FNEG gt R35, R35; R35=-(R35) PA1 FCMP lt R32, R35; if x&lt;-w at vertex 1 then PA1 BCT label; jump to clipping process PA1 FCMP lt R33, R35; if y&lt;-w at vertex 1 then PA1 BCT label; jump to clipping process PA1 FCMP lt R34, R35; if z&lt;-w at vertex 1 then PA1 BCT label; jump to clipping process; PA1 Vertex 2 PA1 FCMP gt R36, R39; if x&gt;w at vertex 2 then PA1 BCT label; jump to clipping process PA1 FCMP gt R37, R39; if y&gt;w at vertex 2 then PA1 BCT label; jump to clipping process PA1 FCMP gt R38, R39; if z&gt;w at vertex 2 then PA1 BCT label; jump to clipping process PA1 FNEG gt R39, R39; R39=-(R39) PA1 FCMP lt R36, R39; if x&lt;-w at vertex 2 then PA1 BCT label; jump to clipping process PA1 FCMP lt R37, R39; if y&lt;-w at vertex 2 then PA1 BCT label; jump to clipping process PA1 FCMP lt R38, R39; if z&lt;-w at vertex 2 then PA1 BCT label; jump to clipping process; PA1 Vertex 3 PA1 FCMP gt R40, R43; if x&gt;w at vertex 3 then PA1 BCT label; jump to clipping process PA1 FCMP gt R41, R43; if y&gt;w at vertex 3 then PA1 BCT label; jump to clipping process PA1 FCMP gt R42, R43; if z&gt;w at vertex 3 then PA1 BCT label; jump to clipping process PA1 FNEG gt R43, R43; R43=-(R43) PA1 FCMP lt R40, R43; if x&lt;-w at vertex 3 then PA1 BCT label; jump to clipping process PA1 FCMP lt R41, R43; if y&lt;-w at vertex 3 then PA1 BCT label; jump to clipping process PA1 FCMP lt R42, R43; if z&lt;-w at vertex 3 then PA1 BCT label; jump to clipping process PA1 End of program list 1
FMAC: Carry out four multiplications in parallel
Example: FMAC R20-R23, R16, R0-R3
FNEG: Invert the sign of a floating-point number
Example: FNEG R0, R1
R0=-(R1)
Examples:
BCT: Branch to a label if TRUE
Example: BCT label
An example of a program for carrying out the geometry translation and clipping test on a triangle with the use of the above instructions will be explained.
A perspective translation matrix is stored as follows: ##EQU3##
Vertex coordinates of the triangle after translation are stored in the following registers:
In this way, the prior art carries out geometry translation by combining comparison instructions each between two numbers and branching instructions. The clipping test of the prior art involves many comparison and branching steps, to deteriorate performance and efficiency.